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ltc1799 1 sn1799 1799fbs one external resistor sets the frequency fast start-up time: < 1ms 1khz to 33mhz frequency range frequency error 1.5% 5khz to 20mhz (t a = 25 c) frequency error 2% 5khz to 20mhz (t a = 0 c to 70 c) 40ppm/ c temperature stability 0.05%/v supply stability 50% 1% duty cycle 1khz to 2mhz 50% 5% duty cycle 2mhz to 20mhz 1ma typical supply current 100 ? cmos output driver operates from a single 2.7v to 5.5v supply low profile (1mm) sot-23 (thinsot? package) 1khz to 33mhz resistor set sot-23 oscillator low cost precision oscillator charge pump driver switching power supply clock reference clocking switched capacitor filters fixed crystal oscillator replacement ceramic oscillator replacement small footprint replacement for econ oscillators the ltc ? 1799 is a precision oscillator that is easy to use and occupies very little pc board space. the oscillator frequency is programmed by a single external resistor (r set ). the ltc1799 has been designed for high accuracy operation ( 1.5% frequency error) without the need for external trim components. the ltc1799 operates with a single 2.7v to 5.5v power supply and provides a rail-to-rail, 50% duty cycle square wave output. the cmos output driver ensures fast rise/fall times and rail-to-rail switching. the frequency-setting resistor can vary from 3k to 1m to select a master oscillator frequency between 100khz and 33mhz (5v supply). the three-state div input determines whether the master clock is divided by 1, 10 or 100 before driving the output, providing three frequency ranges spanning 1khz to 33mhz (5v supply). the ltc1799 features a proprietary feedback loop that linearizes the relationship between r set and frequency, eliminating the need for tables to calculate frequency. the oscillator can be easily pro- grammed using the simple formula outlined below: fmhz k nr n div pin v div pin open div pin gnd osc set =? ? ? ? ? ? ? ? = ? ? ? ? ? = = = + 10 10 100 10 1 , , , , basic connection typical distribution of frequency error, t a = 25 c (5khz f osc 20mhz, v + = 5v) tsot-23 actual size descriptio u features applicatio s u typical applicatio u units (%) 25 20 15 10 5 0 C1.25 C0.75 C0.25 0 0.25 0.75 1.25 frequency error (%) 1799 ta02 v + 1 2 3 5 1khz f osc 33mhz 5v 5v 3k r set 1m 0.1 f 1799 ta01 4 gnd ltc1799 set out div open 10 100 1 thinsot is a trademark of linear technology corporation. protected by u.s. patents including 6342817 and 6614313. , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc1799 2 sn1799 1799fbs supply voltage (v + ) to gnd ........................C 0.3v to 6v div to gnd .................................... C 0.3v to (v + + 0.3v) set to gnd ................................... C 0.3v to (v + + 0.3v) operating temperature range ltc1799c ............................................... 0 c to 70 c ltc1799i ............................................ C 40 c to 85 c ltc1799h ........................................ C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, ja = 256 c/w ltc1799cs5 ltc1799is5 ltc1799hs5 (note 1) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v + = 2.7v to 5.5v, r l =5k, c l = 5pf, unless otherwise noted. all voltages are with respect to gnd. symbol parameter conditions min typ max units ? f frequency accuracy v + = 5v 5khz f 20mhz 0.5 1.5 % 5khz f 20mhz, ltc1799c 2% 5khz f 20mhz, ltc1799i/h 2.5 % (notes 2, 3) 1khz f 5khz 2.5 % 20mhz f 33mhz 2.5 % v + = 3v 5khz f 10mhz 0.5 1.5 % 5khz f 10mhz, ltc1799c 2% 5khz f 10mhz, ltc1799i/h 2.5 % 1khz f 5khz 2.5 % 10mhz f 20mhz 2.5 % r set frequency-setting resistor range ? ? f ? < 1.5% v + = 5v 5 200 k ? v + = 3v 10 200 k ? f max maximum frequency ? ? f ? < 2.5%, pin 4= 0v v + = 5v 33 mhz v + = 3v 20 mhz f min minimum frequency ? ? f ? < 2.5%, pin 4= v + 1 khz ? f/ ? t freq drift over temp (note 3) r set = 31.6k 0.004 %/ c ? f/ ? v freq drift over supply (note 3) v + = 3v to 5v, r set = 31.6k 0.05 0.1 %/v timing jitter pin 4 = v + 0.06 % (note 4) pin 4 = open 0.13 % pin 4 = 0v 0.4 % long-term stability of output frequency 300 ppm/ khr duty cycle (note 7) pin 4 = v + or open (div either by 100 or 10) 49 50 51 % pin 4 = 0v (div by 1), r set = 5k to 200k 45 50 55 % v + operating supply range 2.7 5.5 v i s power supply current r set = 200k, pin 4 = v + , r l = v + = 5v 0.7 1.1 ma r set = 10k, pin 4 = 0v, r l = v + = 5v 2.4 ma v + = 3v 2ma v ih high level div input voltage v + C 0.4 v v il low level div input voltage 0.5 v i div div input current (note 5) pin 4 = v + v + = 5v 5 8 a pin 4 = 0v v + = 5v C8 C5 a top view s5 package 5-lead plastic tsot-23 1 2 3 v + gnd set 5 4 out div s5 part marking ltnd ltne ltnd absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges.
ltc1799 3 sn1799 1799fbs v oh high level output voltage (note 5) v + = 5v, i oh = C 1ma 4.8 4.95 v ltc1799c/i i oh = C 4ma 4.5 4.8 v v + = 5v, i oh = C 1ma 4.75 4.95 v ltc1799h i oh = C 4ma 4.40 4.75 v v + = 3v, i oh = C 1ma 2.7 2.9 v ltc1799c/i i oh = C 4ma 2.2 2.6 v v + = 3v, i oh = C 1ma 2.65 2.90 v ltc1799h i oh = C 4ma 2.10 2.55 v v ol low level output voltage (note 5) v + = 5v, i ol = 1ma 0.05 0.15 v ltc1799c/i i ol = 4ma 0.2 0.4 v v + = 5v, i ol = 1ma 0.05 0.20 v ltc1799h i ol = 4ma 0.25 0.50 v v + = 3v, i ol = 1ma 0.1 0.3 v ltc1799c/i i ol = 4ma 0.4 0.7 v v + = 3v, i ol = 1ma 0.10 0.35 v ltc1799h i ol = 4ma 0.45 0.80 v t r out rise time v + = 5v pin 4 = v + or floating, r l = 14 ns (note 6) pin 4 = 0v, r l = 7ns v + = 3v pin 4 = v + or floating, r l = 19 ns pin 4 = 0v, r l = 11 ns t f out fall time v + = 5v pin 4 = v + or floating, r l = 13 ns (note 6) pin 4 = 0v, r l = 6ns v + = 3v pin 4 = v + or floating, r l = 19 ns pin 4 = 0v, r l = 10 ns symbol parameter conditions min typ max units the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v + = 2.7v to 5.5v, r l =5k, c l = 5pf, pin 4 = v + unless otherwise noted. all voltages are with respect to gnd. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: frequencies near 100khz and 1mhz may be generated using two different values of r set (see the table 1 in the applications information section). for these frequencies, the error is specified under the following assumption: 10k < r set 100k. the frequency accuracy for f osc = 20mhz is guaranteed by design and test correlation. note 3: frequency accuracy is defined as the deviation from the f osc equation. note 4: jitter is the ratio of the peak-to-peak distribution of the period to the mean of the period. this specification is based on characterization and is not 100% tested. note 5: to conform with the logic ic standard convention, current out of a pin is arbitrarily given as a negative value. note 6: output rise and fall times are measured between the 10% and 90% power supply levels. these specifications are based on characterization. note 7: guaranteed by 5v test. electrical characteristics
ltc1799 4 sn1799 1799fbs typical perfor a ce characteristics uw peak-to-peak jitter vs frequency supply current vs output frequency output frequency, f out (hz) 0.2 jitter (%) 0.4 0.7 0.1 0.3 0.5 0.6 1k 100k 1m 10m 100m 1799 g03 0 10k 100 10 1 output frequency, f out (hz) 1.0 supply current (ma) 1.5 2.5 3.0 4.0 4.5 1k 100k 1m 100m 1799 g04 0.5 10k 10m 3.5 2.0 0 100 (5v) 10 (5v) 1 (5v) 1 (3v) 10 (3v) 100 (3v) t a = 25 c c l = 5pf r l = 1m output resistance vs supply voltage supply voltage (v) 2.5 3.0 40 output resistance ( ? ) 80 140 3.5 4.5 5.0 1799 g05 60 120 100 4.0 5.5 6.0 output sinking current output sourcing current t a = 25 c ltc1799 output operating at 20mhz, v s = 5v 1v/div 12.5ns/div 1799 g06 1v/div 25ns/div 1799 g07 v + = 5v, r set = 5k, c l = 10pf v + = 3v, r set = 10k, c l = 10pf ltc1799 output operating at 10mhz, v s = 3v frequency variation vs r set 4 3 2 1 0 C1 C2 C3 C4 1 10 100 1000 1799 g01 r set (k ? ) variation (%) t a = 25 c guaranteed limits apply over 5k to 200k range typical high typical low frequency variation over temperature temperature ( c) C40 variation (%) 0.50 0.25 0.75 1.00 20 60 1799 g02 0 C0.50 C0.25 C20 0 40 80 C0.75 C1.00 r set = 31.6k 1 or 10 or 100 typical high typical low
ltc1799 5 sn1799 1799fbs uu u pi fu ctio s v + (pin 1): voltage supply (2.7v v + 5.5v). this supply must be kept free from noise and ripple. it should be bypassed directly to a ground plane with a 0.1 f capacitor. gnd (pin 2): ground. should be tied to a ground plane for best performance. set (pin 3): frequency-setting resistor input. the value of the resistor connected between this pin and v + deter- mines the oscillator frequency. the voltage on this pin is held by the ltc1799 to approximately 1.13v below the v + voltage. for best performance, use a precision metal film resistor with a value between 10k and 200k and limit the capacitance on this pin to less than 10pf. div (pin 4): divider-setting input. this three-state input selects among three divider settings, determining the value of n in the frequency equation. pin 4 should be tied to gnd for the 1 setting, the highest frequency range. floating pin 4 divides the master oscillator by 10. pin 4 should be tied to v + for the 100 setting, the lowest frequency range. to detect a floating div pin, the ltc1799 attempts to pull the pin toward midsupply. this is realized with two internal current sources, one tied to v + and pin 4 and the other one tied to ground and pin 4. therefore, driving the div pin high requires sourcing approximately 5 a. likewise, driving div low requires sinking 5 a. when pin 4 is floated, preferably it should be bypassed by a 1nf capacitor to ground or it should be surrounded by a ground shield to prevent excessive coupling from other pcb traces. out (pin 5): oscillator output. this pin can drive 5k ? and/or 10pf loads. larger loads may cause inaccuracies due to supply bounce at high frequencies. transients will not cause latchup if the current into/out of the out pin is limited to 50ma. block diagra w C + + C 1 3 gain = 1 v + v bias i res i res r set set gnd master oscillator programmable divider ( 1, 10 or 100) v res = 1.13v 25% (v + C v set ) i res (v + C v set ) ? mo = 100mhz ? k ? ? three-state input detect gnd v + 5 a 1799 bd 5 a out divider select 5 div 4 2
ltc1799 6 sn1799 1799fbs theory of operatio u as shown in the block diagram, the ltc1799s master oscillator is controlled by the ratio of the voltage between the v + and set pins and the current entering the set pin (i res ). the voltage on the set pin is forced to approxi- mately 1.13v below v + by the pmos transistor and its gate bias voltage. this voltage is accurate to 7% at a particular input current and supply voltage (see figure 1). the effective input resistance is approximately 2k. a resistor r set , connected between the v + and set pins, locks together the voltage (v + C v set ) and current, i res , variation. this provides the ltc1799s high precision. the master oscillation frequency reduces to: ?= ? ? ? ? ? ? ? mo set mhz k r 10 10 ? the ltc1799 is optimized for use with resistors between 10k and 200k, corresponding to master oscillator fre- quencies between 0.5mhz and 10mhz. accurate frequen- cies up to 20mhz (r set = 5k) are attainable if the supply voltage is greater than 4v. to extend the output frequency range, the master oscilla- tor signal may be divided by 1, 10 or 100 before driving desired output frequency (hz) 10 r set (k ? ) 100 1k 100k 1m 10m 1799 f02 1 10k 1000 100m 100 10 1 most accurate operation figure 2. r set vs desired output frequency out (pin 5). the divide-by value is determined by the state of the div input (pin 4). tie div to gnd or drive it below 0.5v to select 1. this is the highest frequency range, with the master output frequency passed directly to out. the div pin may be floated or driven to midsupply to select 10, the intermediate frequency range. the lowest fre- quency range, 100, is selected by tying div to v + or driving it to within 0.4v of v + . figure 2 shows the relation- ship between r set , divider setting and output frequency, including the overlapping frequency ranges near 100khz and 1mhz. the cmos output driver has an on resistance that is typically less than 100 ? . in the 1 (high frequency) mode, the rise and fall times are typically 7ns with a 5v supply and 11ns with a 3v supply. these times maintain a clean square wave at 10mhz (20mhz at 5v supply). in the 10 and 100 modes, where the output frequency is much lower, slew rate control circuitry in the output driver increases the rise/fall times to typically 14ns for a 5v supply and 19ns for a 3v supply. the reduced slew rate lowers emi (electromagnetic interference) and supply bounce. i res ( a) 1 0.8 v res = v + C v set 1.2 1.3 1.4 10 100 1000 1799 f01 1.1 1.0 0.9 v + = 5v v + = 3v t a = 25 c figure 1. v + ?v set variation with i res
ltc1799 7 sn1799 1799fbs applicatio s i for atio wu uu figure 3. current controlled oscillator v + 1 2 3 5 v + 0.1 f r set 10k v control 0v to 1.13v 1799 f04 4 gnd n = 1 ltc1799 set out div + C 10mhz n ? osc ? ? ? 1 C v control 1.13v 10k r set () figure 4. voltage controlled oscillator alternative methods of setting the output frequency of the ltc1799 the oscillator may be programmed by any method that sources a current into the set pin (pin 3). the circuit in figure 3 sets the oscillator frequency using a program- mable current source and in the expression for f osc , the resistor r set is replaced by the ratio of 1.13v/i control . as already explained in the theory of operation, the voltage difference between v + and set is approximately 1.13v, therefore, the figure 3 circuit is less accurate than if a resistor controls the oscillator frequency. figure 4 shows the ltc1799 configured as a vco. a voltage source is connected in series with an external 10k resistor. the output frequency, f osc , will vary with v control , that is the voltage source connected between v + and the set pin. again, this circuit decouples the relationship between the input current and the voltage between v + and set; the frequency accuracy will be degraded. the oscillator frequency, however, will mono- tonically increase with decreasing v control . selecting the divider setting and resistor the ltc1799s master oscillator has a frequency range spanning 0.1mhz to 33mhz. however, accuracy may suffer if the master oscillator is operated at greater than 10mhz with a supply voltage lower than 4v. a program- mable divider extends the frequency range to greater than three decades. table 1 describes the recommended fre- quencies for each divider setting. note that the ranges overlap; at some frequencies there are two divider/resistor combinations that result in the desired frequency. in general, any given oscillator frequency (f osc ) should be obtained using the lowest master oscillator frequency. lower master oscillator frequencies use less power and are more accurate. for instance, f osc = 100khz can be obtained by either r set = 10k, n = 100, master oscillator = 10mhz or r set = 100k, n = 10, master oscillator = 1mhz. the r set = 100k is preferred for lower power and better accuracy. table 1. frequency range vs divider setting divider setting frequency range 1 ? div (pin 4) = gnd > 500khz * 10 ? div (pin 4) = floating 50khz to 1mhz 100 ? div (pin 4) = v + < 100khz * at master oscillator frequencies greater than 10mhz (r set < 10k ? ), the ltc1799 may suffer reduced accuracy with a supply voltage less than 4v. after choosing the proper divider setting, determine the correct frequency-setting resistor. because of the linear correspondence between oscillation period and resis- tance, a simple equation relates resistance with frequency. rk mhz nf set osc = ? ? ? ? ? ? ? ? ? ? ? 10 10 100 10 1 ? ? , n = (r setmin = 3k (5v supply), 5k (3v supply), r setmax = 1m) any resistor, r set , tolerance adds to the inaccuracy of the oscillator, f osc . v + 1 2 3 5 400khz to 21mhz (approximate, see text) v + 0.1 f i control 5 a to 200 a 1799 f03 4 gnd n = 1 ltc1799 set out div 10mhz n ? osc ? ??i control i control expressed in (a) 10k ? 1.13v
ltc1799 8 sn1799 1799fbs supply voltage (v) 2.5 C0.05 frequency deviation (%) 0 0.05 0.10 0.15 3.0 3.5 4.0 4.5 1799 f05 5.0 5.5 85 c C40 c 25 c r set = 31.6k pin 4 = floating ( 10) figure 5. supply sensitivity time after power applied ( s) 0 60 50 40 30 20 10 0 C10 300 500 1799 f06 100 200 400 600 frequency error (%) 10k 31.6k 200k t a = 25 c v + = 5v power supply rejection low frequency supply rejection (voltage coefficient) figure 5 shows the output frequency sensitivity to power supply voltage at several different temperatures. the ltc1799 has a conservative guaranteed voltage coeffi- cient of 0.1%/v but, as figure 5 shows, the typical supply sensitivity is lower. start-up time the start-up time and settling time to within 1% of the final value can be estimated by t start ? r set (2.8 s/k ? ) + 20 s. note the start-up time depends on r set and it is independent from the setting of the divider pin. for in- stance with r set = 50k, the ltc1799 will settle with 1% of its 200khz final value (n = 10) in approximately 160 s. figure 6 shows start-up times for various r set resistors. figure 7 shows an application where a second set resistor r set2 is connected in parallel with set resistor r set1 via switch s1. when switch s1 is open, the output frequency of the ltc1799 depends on the value of the resistor r set1 . when switch s1 is closed, the output frequency of the ltc1799 depends on the value of the parallel combination of r set1 and r set2 . the start-up time and settling time of the ltc1799 with switch s1 open (or closed) is described by t start shown above. once the ltc1799 starts and settles, and switch s1 closes (or opens), the ltc1799 will settle to its new output frequency within approximately 25 s. figure 6. start-up time applicatio s i for atio wu uu v + 1 2 r set1 r set2 3 s1 5 v + 1799 f07 4 gnd ltc1799 3v or 5v set out div 10 100 1 f osc = 10mhz ? or () 10k n ? r set1 f osc = 10mhz ? () 10k n ? r set1 //r set2 figure 7 high frequency power supply rejection the accuracy of the ltc1799 may be affected when its power supply generates significant noise with frequency contents in the vicinity of the programmed value of f osc . if a switching power supply is used to power up the ltc1799, and if the ripple of the power supply is more than a few tens of millivolts, make sure the switching frequency and its harmonics are not related to the output frequency of the ltc1799. otherwise, the oscillator may show an additional 0.1% to 0.2% of frequency error. if the ltc1799 is powered by a switching regulator and the switching frequency or its harmonics coincide with the output frequency of the ltc1799, the jitter of the oscillator output may be affected. this phenomenon will become noticeable if the switching regulator exhibits ripples be- yond 30mv.
ltc1799 9 sn1799 1799fbs applicatio s i for atio wu uu jitter the typical jitter is listed in the electrical characteristics and shown in the typical performance characteristics. these specifications assume that the capacitance on set (pin 3) is limited to less than 10pf, as suggested in the pin functions description. if this requirement is not met, the jitter will increase. for more information, contact linear technology applications group. a ground referenced voltage controlled oscillator the ltc1799 output frequency can also be programmed by steering current in or out of the set pin, as conceptually shown in figure 8. this technique can degrade accuracy as the ratio of (v + C v set ) / i res is no longer uniquely dependent of the value of r set , as shown in the ltc1799 block diagram. this loss of accuracy will become notice- able when the magnitude of i prog is comparable to i res . the frequency variation of the ltc1799 is still monotonic. figure 9 shows how to implement the concept shown in figure 8 by connecting a second resistor, r in , between the set pin and a ground referenced voltage source, v in . for a given power supply voltage in figure 9, the output frequency of the ltc1799 is a function of v in , r in , r set and (v + C v set ) = v res : f mhz n k rr vv v r r osc in set in res in set = + ? () + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 10 10 1 1 1 ?? ? (1) when v in = v + , the output frequency of the ltc1799 assumes the highest value and it is set by the parallel combination of r in and r set . also note, the output fre- quency, f osc , is independent of the value of v res = (v + C v set ) so the accuracy of f osc is within the data sheet limits. when v in is less than v + , and especially when v in ap- proaches the ground potential, the oscillator frequency, f osc , assumes its lowest value and its accuracy is affected by the change of v res = (v + C v set ). at 25 c v res varies by 8%, assuming the variation of v + is 5%. the tem- perature coefficient of v res is 0.02%/ c. by manipulating the algebraic relation for f osc above, a simple algorithm can be derived to set the values of external resistors r set and r in , as shown in figure 9. 1. choose the desired value of the maximum oscillator frequency, f osc(max) , occurring at maximum input volt- age v in(max) v + . 2. set the desired value of the minimum oscillator fre- quency, f osc(min) , occurring at minimum input voltage v in(min) 0. 3. choose v res = 1.1 and calculate the ratio of r in /r set from the following: r r vv f f vv v f f in set in max osc max osc min in min res osc max osc min = ? () ? ? ? ? ? ? ? ? () () ? ? ? ? ? ? ? ? ? ? ++ () () () () () () 1 1 (2) figure 9. implementation of concept shown in figure 8 figure 8. concept for programming via current steering v + 1 2 r set v res r in v in 3 5 5v v + 1799 f09 4 gnd ltc1799 0.1 f f osc open set out div 10 100 1 + C + C v + 1 2 r set i pr 3 5 5v v + 1799 f08 4 gnd ltc1799 0.1 f open set out div 10 100 1 i res
ltc1799 10 sn1799 1799fbs typical applicatio s u 3v r set 1 2 16 10 7 8 9 15 3 4 5 6 11 12 13 14 clock a enable a v dd enable b reset a v ss clock b reset b q1a q2a q3a q4a q1b q2b q3b q4b 74hc4520 f osc 2 4 8 16 32 64 128 256 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v + nc v + sa lpa bpa hpa/na inv a clk agnd v C sb lpb bpb hpb/nb inv b ltc1067-50 3v c2 0.1 f c1 0.1 f c3 0.1 f c4 1 f r61 10k r51 5.11k r31 51.1k r21 20k r h1 249k r l1 51.1k clock-tunable lowpass filter with a stopband notch at the 3rd harmonic 3v r62 14k r52 5.11k r32 51.1k r22 20k sinewave out 1799 ta05 r11 100k v + gnd ltc1799 set out 1 2 3 5 3v 4 3v, n = 100 open, n = 10 800hz f sine 8khz, n = 10 80hz f sine 800hz, n = 100 div f osc 64 f osc 64 () ? 3 f sine = ? 10mhz n 10k 64r set sw1 low power 80hz to 8khz sine wave generator (i q < 4ma) once r in /r set is known, calculate r set from: r mhz n k f vvv r r v r r set osc max in max res in set res in set = ? () ++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 10 10 1 ?? () () (3) maximum vco modulation bandwidth the maximum vco modulation bandwidth is 10khz; that is, the ltc6900 will respond to changes in v in at a rate up to 25khz. in lower frequency applications however, the modulation frequency may need to be limited to a lower rate to prevent an increase in output jitter. this lower limit is the master oscillator frequency divided by 20, (f osc /20). in general, for minimum output jitter the modulation frequency should be limited to f osc /20 or 10khz, which- ever is less. for best performance at all frequencies, the value for f osc should be the master oscillator frequency (n = 1) when v in is at the lowest level. table 2. variation of v res for various values of r in || r set r in || r set (v in = v + )v res , v + = 3v v res , v + = 5v 10k 0.98v 1.06v 20k 1.03v 1.11v 40k 1.09v 1.17v 80k 1.13v 1.21v 160k 1.16v 1.24v v res = voltage across r set note: all of the calculations above assume v res = 1.1v, although v res 1.1v. for completeness, table 2 shows the variation of vres against various parallel combinations of r in and r set (v in = v + ). calulate first with v res 1.1v, then use table 2 to get a better approximation of v res , then recalculate the resistor values using the new value for v res .
ltc1799 11 sn1799 1799fbs package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 typ 5 plcs (note 3) datum a 0.09 C 0.20 (note 3) s5 tsot-23 0302 pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635)
ltc1799 12 sn1799 1799fbs linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2001 lt/tp 0804 1k rev b ?printed in usa shutting down the ltc1799 v + 1 2 3 5 r1 10k on/shdn 5v 74ac04 c1 0.1 f 1799 ta08 4 out gnd ltc1799 set out div temperature-to-frequency converter v + 1 2 3 5 f osc = ? 10mhz 10 5v r t 100k thermistor c1 0.1 f 1799 ta03 4 r t : ysi 44011 800 765-4974 gnd ltc1799 set out div 10k r t 1799 ta04 1400 1200 1000 800 600 400 200 0 C20C100 102030405060708090 temperature ( c) frequency (khz) max typ min output frequency vs temperature typical applicatio s u

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